Cut-off frequency (fT) and maximum oscillation frequency (fmax) are the most representative measures of operation speed for high-speed transistors. Hence, the design and optimization efforts for high-speed transistors are mostly directed towards maximization of the aforementioned parameters. As the emitter dimension is shrinking to improve bipolar transistor performance, the parasitic resistance and capacitance are becoming larger and more significant in determining the transistor operation speed, i.e., fT and fmax.
For a small emitter, the emitter contact dimension needs to be large to maintain low contact resistance and high current operation capability. As a result, the emitter contact area needs to be defined by a lithographic level of dimension X, as shown in FIG. 1, which is larger than the emitter dimension; FIG. 1 is a cross-sectional view of a bipolar transistor that is made using a prior art process. This results in a T-shaped emitter with excess top regions of dimension Y that prevents the raised extrinsic base silicide edge from being extended closer and self-aligned to the emitter edge and increases the overlap area between the emitter and the extrinsic base.
The limitation of extending the silicide closer to the emitter leads to high base resistance (Rb). More specifically, the current has to traverse the polysilicon diagonally to reach the silicide edge, which results in a high base resistance due to its component Rb(poly) of the non-silicided polysilicon, as shown in FIG. 1. Rb(poly) can be as high as 36% of the total base resistance. In addition, the excess top regions of the emitter result in a higher emitter-to-base capacitance (Ceb) due to the additional component Ceb (TEOS) across the isolation TEOS as shown in FIG. 1.
In view of the drawbacks mentioned with prior art bipolar transistors, there is a need for developing a new and improved bipolar transistor in which resistance and capacitance have been substantially reduced in order to improve the transistor high-speed performance.